The present application relates generally to slew rate control circuitry, and more specifically to circuitry for controlling the slew rate of switched power supplies.
Slew rate control circuitry is frequently employed in conjunction with switched power supplies. For example, the slew rate of a switched power supply on a mother printed circuit (PC) card is often controlled to limit the in-rush current charging bulk decoupling capacitors on one or more daughter PC cards. Such slew rate control of the mother PC card power supply is necessary because excessive in-rush current can (1) adversely affect the operation of the switched power supply, (2) trigger unwanted system resets, and/or (3) disrupt system processor operation.
A conventional approach for controlling the slew rate of a switched power supply employs a source-follower circuit configuration, in which a capacitor is connected to the gate of a Field Effect Transistor (FET), an input supply voltage is connected to the drain of the FET, and an output supply voltage is provided across a load connected to the source of the FET. The capacitor is charged by a constant current to provide a linear voltage ramp to the gate of the FET. Because the voltage on the source of the FET follows the linear voltage ramp on the gate of the FET, slew rate control of the output supply voltage is achieved. In the event it is desired to control the slew rate of a positive output supply voltage, the source-follower typically includes an NMOS FET. In the event the slew rate of a negative output supply voltage is to be controlled, the source-follower typically includes a PMOS FET.
Although the conventional source-follower circuit configuration described above has been successfully employed to control the slew rate of switched power supplies, the source-follower approach has several drawbacks. For example, the source-follower requires a charging capacitor, which can be bulky and expensive. Further, when controlling the slew rate of a negative output supply voltage, the source-follower requires a PMOS FET, which can also be an expensive circuit component.
Instead of using a PMOS FET to control the slew rate of the negative output supply, an NMOS FET may be employed. For example, another conventional circuit configuration has the negative input supply voltage connected to the source of the NMOS FET, the negative output supply voltage provided across a load connected to the drain of the NMOS FET, and a Miller capacitor connected between the gate and the drain of the NMOS FET. As in the conventional source-follower circuit configuration, a constant current source is used to charge the Miller capacitor. However, this alternative circuit configuration also has drawbacks due at least in part to the bulky and expensive Miller capacitor.
It would therefore be desirable to have circuitry for controlling the slew rate of switched power supplies that avoids the drawbacks of the above-described circuit configurations.